`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/06/23 20:11:48
// Design Name: 
// Module Name: ifetch
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module ifetch(
    input clk,
    input rst,
    input [31:0] imm,
    input [31:0] alu_c,
    input [1:0] npc_sel,
    output [31:0] inst,
    output [31:0] pc,
    output [31:0] pc4
    );

wire [31:0] npc_out;
wire [31:0] instruction;
    
PC pc_0(.rst(rst),
        .clk(clk),
        .din(npc_out),
        .pc(pc)
       );
       
NPC npc_0(.rst(rst),
          .pc(pc),
          .imm(imm),
          .alu_c(alu_c),
          .npc_sel(npc_sel),
          .npc(npc_out),
          .pc4(pc4)
         );
         
prgrom imem(.a(pc[15:2]),
            .spo(inst) 
           );


endmodule
